1. Field of the Invention
The invention relates to a chip structure with a passive device and a method for forming the same. More particularly, the invention relates to a chip structure having a passive device with high performance and high quality and a method for forming the same.
2. Description of the Related Art
Information products are playing important roles in today's competitive society. With the evolution of the information products and the introduction of the concept of integrating various circuit designs, the latest single chip, generally, provides more functions than the former one. After integration, the dimension of the circuits is reduced and the majority of the signals are being transmitted within a single chip. As a result, paths for transmitting signals are reduced and the performance of the chip is improved.
In general, a circuit often works with some passive devices. Conventional passive devices are positioned inside a chip or on a printed circuit board. In the first case, as passive devices are formed inside the chip, they are formed in or over a semiconductor substrate during the formation of electronic devices, whose methods comprise a physical-vapor-deposition (PVD) process, a chemical-vapor-deposition (CVD) process, and a photolithography-etching process. In the second case, as the passive devices are being placed on a printed circuit board, they are bonded onto the printed circuit board using surface-mounting technology (SMT). In the latest advancement of the technology, the concept related to placing passive devices over an IC passivation layer is presented in U.S. Pat. No. 6,303,423, U.S. Pat. No. 6,455,885, U.S. Pat. No. 6,489,647, U.S. Pat. No. 6,489,656, and U.S. Pat. No. 6,515,369.
Wherever the passive devices are disposed, both merits and demerits exist. When the passive devices are formed in the chip, a resistor with high quality and high accuracy can be formed using the concurrent semiconductor process. A capacitor having a dielectric layer that is as thin as a few angstroms can be formed using a chemical-vapor-deposition process and thus the capacitor with high accuracy can be provided. However, in the case that an inductor is formed in a chip, an eddy current occurs in the silicon semiconductor substrate, due to the electromagnetic field generated by the inductors, which dramatically reduces the quality factor of the inductor (Q value). The parasitic capacitance between the inductor and the underlying silicon semiconductor substrate induces a serious negative impact on a LC circuit with the inductors. Furthermore, the electromagnetic field generated by the inductors would adversely impact the performance of other electronic devices that are located in the vicinity of the inductors.
When the passive devices are formed on the passivation layer of the chip, the process is generally performed in a bump fab. The bump fab can not provide a process with high image resolution whereby a resistor and a capacitor are formed and therefore the dimension of the resistor and the capacitor is inaccurate. The resistance value of the resistor and the capacitance value of the capacitor can not be controlled within a small tolerance. Generally, a bump fab does not have a capability of forming a film using a chemical-vapor-deposition process and thus a thin dielectric layer can not be formed for the capacitor. As a result, the capacitor with large capacitance value can not be formed in a bump fab.